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For the Inventor, By the Inventor

Singapore, Singapore

David Hu

This inventor holds 6 USPTO granted patents. Top assignee: Nano Silicon Pte. Ltd.. Active years: 2002-2006.

IDiyas Innovation Intelligence. (2026). Inventor Profile: David Hu. Retrieved from https://idiyas.com/inventor/david-hu-151pv8uw

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 6

% Patents Active = 83.3

Average Co-Inventor Count = 2.0

ph-index = 3

Forward Citations = 22(Granted Patents)


Company Filing History:

goldMedal6 out of 9 
 
Nano Silicon Pte. Ltd.
 patents

Years Active: 2002-2006

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6 patents (USPTO):Explore Patents
1. 7154150 - Low triggering N MOS transistor for ESD protection working under fully silicided process without silicide blocks (2006-12-26),
2. 6787880 - ESD parasitic bipolar transistors with high resistivity regions in the collector (2004-09-07),
3. 6787856 - Low triggering N MOS transistor for electrostatic discharge protection device (2004-09-07),
4. 6589833 - ESD parasitic bipolar transistors with high resistivity regions in the collector (2003-07-08),
5. 6507090 - Fully silicide cascaded linked electrostatic discharge protection (2003-01-14),
6. 6444510 - Low triggering N MOS transistor for ESD protection working under fully silicided process without silicide blocks (2002-09-03),

Title: David Hu - Innovator in ESD Protection Technology

Introduction

David Hu is a prominent inventor based in Singapore, known for his contributions to electrostatic discharge (ESD) protection technology. With a total of 6 patents to his name, he has made significant advancements in the field of semiconductor devices.

Latest Patents

His latest patents include innovative designs for low triggering N MOS transistors aimed at enhancing ESD protection. One of his notable inventions is a device and method utilizing parasitic bipolar transistors that are silicided. The first embodiment features a parasitic Bipolar Junction Transistor composed of n+/n−/p−/n−/n+ regions. The emitter is formed from the second N+ region and the second N− well, while the parasitic base is created by the p− substrate or well. The collector is constructed from the first well and the first n+ region. This design benefits from a lower trigger voltage due to reduced crossover concentrations at the junctions. The subsequent embodiments build upon this foundation, introducing additional gates and regions to further enhance the device's performance.

Career Highlights

David Hu is currently employed at Nano Silicon Pte. Ltd., where he continues to innovate in the field of semiconductor technology. His work focuses on developing advanced ESD protection devices that are crucial for modern electronic applications.

Collaborations

He collaborates with Jun Cai, leveraging their combined expertise to push the boundaries of ESD protection technology.

Conclusion

David Hu's contributions to the field of ESD protection through his innovative patents and collaborative efforts mark him as a significant figure in semiconductor technology. His work continues to influence the development of safer and more efficient electronic devices.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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