Nano Silicon Pte. Ltd.

David Hu

Jun Cai

An ESD device and method using parasitic bipolar transistors that are silicided. The first embodiment is a parasitic Bipolar Junction Transistor comprised of n+/n&#x2212;/p&#x2212;/n&#x2212;/n+ regions. The emitter is formed of the second N+ region and the second N&#x2212; well. The parasitic base is formed by the p&#x2212; substrate or well. The collector is formed of the first well and the first n+ region. The benefit of the first embodiment is the trigger voltage is lower because the junction between the n&#x2212; well (emitter) and P&#x2212; substrate (base) and the junction between P&#x2212; substrate (base) and the n&#x2212; well have lower cross over concentrations. The second embodiment is similar to the first embodiment with the addition of the first gate. The first gate is preferably connected to the first n+ region and the Vpad. The third embodiment contains the same elements as the second embodiment with the addition of a third n+ region. The third n+ region is preferably shorted (or connected) to the first p+ region and the second n+ region. The third embodiment forms a second NPN parasitic bipolar using the third N+ region as an emitter. The forth embodiment contains the same elements as the third embodiment with the addition of a second gate over the first isolation region. The second gate is preferably connected to the third n+ region to the first p+ region and the second n+ region. The gate changes the electrical characteristics of the first parasitic bipolar transistor.

Low triggering N MOS transistor for ESD protection working under fully silicided process without silicide blocks

A method and a structure for a parasitic bipolar silicided ESD device that has high resistivity regions within the collector of the parasitic NPN. The device has the structure of a N-MOS transistor and a substrate contact. The device preferably has silicide regions over the doped regions. The invention has two types of high resistivity regions: 1) isolation regions (e.g., oxide shallow trench isolation (STI)) and 2) undoped or lightly doped regions (e.g., channel regions). The channel regions can have gates thereover and the gates can be charged. Also, optionally a n well (n minus well) can be formed under the collector. The high resistivity regions increase the collector resistivity thereby improving the performance of the parasitic bipolar ESD device.

ESD parasitic bipolar transistors with high resistivity regions in the collector

An ESD device and method using parasitic bipolar transistors that are silicided. The first embodiment is a parasitic Bipolar Junction Transistor comprised of n&plus;/n&minus;/p&minus;/n&minus;/n&plus; regions. The emitter is formed of the second N&plus; region and the second N&minus; well. The parasitic base is formed by the p&minus; substrate or well. The collector is formed of the first well and the first n&plus; region. The benefit of the first embodiment is the trigger voltage is lower because the junction between the n&minus; well (emitter) and P&minus; substrate (base) and the junction between P&minus; substrate (base) and the n-well have lower cross over concentrations. The second embodiment is similar to the first embodiment with the addition of the first gate. The first gate is preferably connected to the first n&plus; region and the Vpad. The third embodiment contains the same elements as the second embodiment with the addition of a third n&plus; region. The third n&plus; region is preferably shorted (or connected) to the first p&plus; region and the second n&plus; region. The third embodiment forms a second NPN parasitic bipolar using the third N&plus; region as an emitter. The forth embodiment contains the same elements as the third embodiment with the addition of a second gate over the first isolation region. The second gate is preferably connected to the third n&plus; region to the first p&plus; region and the second n&plus; region. The gate changes the electrical characteristics of the first parasitic bipolar transistor.

Low triggering N MOS transistor for electrostatic discharge protection device

A method and a structure of for an Electro Static Discharge (ESD) device that is silicided. There are three preferred embodiments of the invention. The first embodiment has a N/P/N structure. The emitter, the collector and the substrate form a parasitic transistor and the substrate is connected to the p&plus; diffusion region. The emitter and the substrate act as a first diode D and the collector and the substrate act as a second diode D The second embodiment has a first N&plus; well between a second n&plus; (collector) region and a P&plus; base region. The Vt is controlled by the dopant profiles of the P&plus; base and the n&minus; first well where they intersect. The third embodiment is similar to the second embodiment, but the n&minus; well covers all of drain. A parasitic NPN bipolar transistor comprises: an emitter, a parasitic base and a drain. The emitter is formed by the first n&plus; region. The parasitic base is formed by the p-substrate. The collector is formed by the second n&plus; region and the first n&minus; well. The Vt is controlled by the dopant profiles of the P&plus; base and the n&minus; first well where they intersect.

Fully silicide cascaded linked electrostatic discharge protection

An ESD device and method using parasitic bipolar transistors that are silicided. The first embodiment is a parasitic Bipolar Junction Transistor comprised of n&plus;/n&minus;/p&minus;/n&minus;/n&plus; regions. The emitter is formed of the second N&plus; region and the second N&minus; well. The parasitic base is formed by the p&minus; substrate or well. The collector is formed of the first well and the first n&plus; region. The benefit of the first embodiment is the trigger voltage is lower because the junction between the n&minus; well (emitter) and P&minus; substrate (base) and the junction between P&minus; substrate (base) and the n&minus; well have lower cross over concentrations. The second embodiment is similar to the first embodiment with the addition of the first gate. The first gate is preferably connected to the first n&plus; region and the Vpad. The third embodiment contains the same elements as the second embodiment with the addition of a third n&plus; region. The third n&plus; region is preferably shorted (or connected) to the first p&plus; region and the second n&plus; region. The third embodiment forms a second NPN parasitic bipolar using the third N&plus; region as an emitter. The forth embodiment contains the same elements as the third embodiment with the addition of a second gate over the first isolation region. The second gate is preferably connected to the third n&plus; region to the first p&plus; region and the second n&plus; region. The gate changes the electrical characteristics of the first parasitic bipolar transistor.

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Singapore, Singapore

David Hu