Natrampalli, India

David Elayaraj Samaraj

This inventor holds 1 USPTO granted patent. Top assignee: Intel Corporation. Active years: 2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: David Elayaraj Samaraj. Retrieved from https://idiyas.com/inventor/david-elayaraj-samaraj

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank

Average Co-Inventor Count = 1.0

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Company Filing History:


Years Active: 2026

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1 patent (USPTO):Explore Patents

Title: David Elayaraj Samaraj and Circuit-Board Interference Reduction

Introduction

David Elayaraj Samaraj is an inventor based in Natrampalli, India, associated with Intel Corporation. His patent work addresses ways to reduce radiofrequency interference and noise in circuit boards.

Latest Patents

Samaraj is credited with 1 patent: “Technologies for Reducing the Impact of Radiofrequency Interference on a Circuit Board.” The invention describes applying conductive ink in a silk-screen layer over a circuit board’s solder mask. The ink forms shield regions beneath and near inductors or power-plane routes, and these regions may connect to the board’s ground plane.

By partially shielding nearby traces, the design can reduce induced noise and allow high-speed input/output traces to be routed closer to inductors. This may help reduce circuit-board size, layer count, or cost. In some embodiments, the shields also limit emissions from the power plane, helping reduce interference with device antennas.

Career Highlights

Samaraj’s listed work is associated with Intel Corporation. His patent focuses on practical circuit-board design techniques for managing interference while supporting compact and cost-conscious layouts.

Collaborations

Rakesh Yedri is identified as a coworker. The available information does not specify his role in the patent or the nature of their collaboration.

Conclusion

David Elayaraj Samaraj’s patent describes conductive shielding as a way to reduce circuit-board noise, support closer trace routing, and potentially improve device layout and cost.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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