Kuching, Malaysia

Darryl Wong Jun Chen

This inventor holds 1 USPTO granted patent. Top assignee: Sandisk Technologies Inc.. Active years: 2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Darryl Wong Jun Chen. Retrieved from https://idiyas.com/inventor/darryl-wong-jun-chen

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank

Average Co-Inventor Count = 1.0

ph-index = 1


Company Filing History:


Years Active: 2026

Loading Chart...
1 patent (USPTO):Explore Patents

Title: Darryl Wong Jun Chen: Semiconductor Packaging Innovation

Introduction

Darryl Wong Jun Chen is an inventor associated with Kuching, Malaysia, and Sandisk Technologies Inc. His listed patent concerns improving the reliability of semiconductor packaging by reducing electrical shorts during manufacturing.

Latest Patents

Chen is credited with 1 patent, titled “Selective Wire Coating During Wire Bonding.” The invention describes coating a selected subset of bond wires with an electrically insulating polymer. This coating is intended to reduce electrical shorts that can occur when molding compound flow causes wires to sweep into contact during encapsulation.

The patent also describes selecting wires for coating according to criteria that identify those with a relatively high risk of causing shorts. A specialized wire-bonding tool can produce both polymer-coated and uncoated bond wires.

Career Highlights

Chen’s listed work at Sandisk Technologies Inc. is associated with semiconductor manufacturing and packaging. The patent’s selective-coating approach addresses a specific production challenge while allowing other bond wires to remain uncoated.

Collaborations

Jiun Dong Loeh and Muhammad Farhan Taufiq Mohamad Helmi are identified as Chen’s coworkers. The provided information does not specify their roles in the patent or the invention.

Conclusion

Darryl Wong Jun Chen’s listed patent presents a targeted wire-bonding technique designed to help prevent molding-related electrical shorts in semiconductor devices.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
Loading…