Turin, Italy

Dante Trevisan

This inventor holds 1 USPTO granted patent. Top assignee: Cselt-Centro Studi E Laboratori Telecomunicazioni S.p.a.. Active years: 1986.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Dante Trevisan. Retrieved from https://idiyas.com/inventor/dante-trevisan

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


% Patents Active = 100.0

Average Co-Inventor Count = 2.0

ph-index = 1

Forward Citations = 7(Granted Patents)


Company Filing History:


Years Active: 1986

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1 patent (USPTO):Explore Patents

Title: The Innovative Mind of Dante Trevisan

Introduction

Dante Trevisan is a notable inventor based in Turin, Italy. He has made significant contributions to the field of semiconductor technology. His work focuses on the development of integrated-circuit gate arrays, which are essential components in modern electronics.

Latest Patents

Dante Trevisan holds a patent for a "Unit cell for integrated-circuit gate arrays." This invention describes a unit cell for a prefabricated semiconductor chip that can be transformed into an array of logic gates through selective metallization. The design features two complementary pairs of MOSFETs positioned in quadrants of a rectangular substrate area. The external gate contacts are strategically placed in headers along the minor sides of the rectangle, facilitating efficient functionality.

Career Highlights

Trevisan is associated with CSELT - Centro Studi e Laboratori Telecomunicazioni S.p.A., where he has been instrumental in advancing telecommunications technology. His innovative approach has led to the development of cutting-edge solutions in the semiconductor industry.

Collaborations

Dante Trevisan has collaborated with Marco Gandini, working together to push the boundaries of technology and innovation in their field.

Conclusion

Dante Trevisan's contributions to integrated-circuit technology exemplify the spirit of innovation. His patent and work at CSELT highlight his role as a key figure in the advancement of semiconductor technology.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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