Unit cell for integrated-circuit gate arrays

Abstract

A unit cell for a prefabricated semiconductor chip, to be converted into an array of logic gates by selective metallization, comprises two complementary pairs of MOSFETs occupying respective quadrants of a rectangular substrate area, with external gate contacts disposed in respective headers extending along the minor sides of the rectangle. Each header further contains two external channel (source or drain) contacts which with the two external gate contacts form a group of four input/output contacts. Two metallic strips serving as supply buses, parallel to the minor sides, are separated from the two headers by relatively narrow substrate zones so as to define a relatively wide central region between them. The external gate contacts of two diagonally opposite MOSFETs are interconnected by a strip of polycrystalline silicon crossing the supply buses, each of these buses being also crossed by a respective polysilicon strip linking the other external gate contact of the proximal contact group with an internal gate contact located in the central region. The two external channel contacts in each header, which are disposed near the corners of the cell area, are paired with respective internal contacts also located in the central region on correspondingly doped substrate portions, as are two other internal channel contacts each common to a respective transistor pair and located in an inner terminal section of its respective transistor pair which is separated from the associated outer terminal sections thereof by the polysilicon strips running between the associated external and internal gate contacts. A further polysilicon strip extends along one of the major sides of the cell area to facilitate certain intercell connections.