Daniel J Liao is a prominent inventor based in Pleasanton, CA. He has made significant contributions to the field of semiconductor technology, holding 2 patents that showcase his innovative approach to solving complex engineering challenges.

Latest Patents

One of his latest patents is titled "Conductor capacitance reduction in integrated circuits." This invention presents a passive semiconductor structure designed to reduce the mutual capacitance between parallel conductors. The structure features two parallel conductors that are separated from a substrate by a first dielectric layer and covered by a second dielectric layer. Notably, the second dielectric layer contains a cavity formed between these conductors, which effectively reduces the relative dielectric constant of the medium between them.

Another significant patent by Liao is the "Method for preventing the exposure of borophosphosilicate glass." This invention outlines a semiconductor fabrication process that deposits an oxide layer after creating contact openings in a BPSG layer and before a contact reflow step. The oxide layer plays a crucial role in allowing implant dopants to be properly activated during the contact reflow step, while preventing excessive reflow of the BPSG.

Career Highlights

Daniel J Liao is currently employed at Integrated Device Technology, Inc., where he continues to push the boundaries of semiconductor innovation. His work has been instrumental in advancing the technology used in integrated circuits.

Collaborations

Liao collaborates with talented individuals such as Chuen-Der Lien and Jimmy J Lee, contributing to a dynamic and innovative work environment.

Conclusion

Daniel J Liao's contributions to semiconductor technology through his patents reflect his commitment to innovation and excellence in engineering. His work continues to influence the field and inspire future advancements.