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For the Inventor, By the Inventor

Kawasaki, Japan

Dai Nakamura

This inventor holds 26 USPTO granted patents and 1 published patent application, primarily in Semiconductor Memory. Top assignees: Kabushiki Kaisha Toshiba, Kioxia Corporation, Toshiba Memory Corporation. Active years: 2010-2025.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Dai Nakamura. Retrieved from https://idiyas.com/inventor/dai-nakamura

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 26 

% Patents Active = 76.9

Average Co-Inventor Count = 2.7

ph-index = 6

Forward Citations = 101(Granted Patents)


Location History:

  • Kawasaki-ken, JP (2012)
  • Fujisawa, JP (2012 - 2014)
  • Fujisawa Kanagawa, JP (2021)
  • Kawasaki, JP (2010 - 2023)

Company Filing History:

goldMedal14 out of 53,276 
 
Kabushiki Kaisha Toshiba
 patents
silverMedal7 out of 3,204 
 
Kioxia Corporation
 patents
bronzeMedal5 out of 2,955 
 
Toshiba Memory Corporation
 patents

Years Active: 2010-2025

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Areas of Expertise:
Non-Volatile Storage
Semiconductor Memory
Charge Accumulation Layer
Control Gate
NAND Flash Memory
Power Source Voltage Generator
Current Detection Circuit
Erasing Method
26 patents (USPTO):Explore Patents
1. RE50512 - Non-volatile semiconductor storage device (2025-07-29),
2. 12237014 - Semiconductor memory device with memory cells each including a charge accumulation layer and a control gate (2025-02-25),
3. 12197732 - Memory system (2025-01-14),
4. 11610630 - Semiconductor memory device with memory cells each including a charge accumulation layer and a control gate (2023-03-21),
5. RE49274 - Non-volatile semiconductor storage device (2022-10-31),
6. 11209846 - Semiconductor device having plural power source voltage generators, and voltage supplying method (2021-12-28),
7. 11139039 - Memory device having memory cell and current detection circuit (2021-10-05),
8. 10978151 - Semiconductor memory device with memory cells each including a charge accumulation layer and a control gate (2021-04-13),
9. 10431309 - Semiconductor memory device with memory cells each including a charge accumulation layer and a control gate (2019-10-01),
10. 10304538 - Semiconductor memory device with memory cells each including a charge accumulation layer and a control gate (2019-05-28),
11. RE47355 - Non-volatile semiconductor storage device (2019-04-15),
12. 10049745 - Semiconductor memory device with memory cells each including a charge accumulation layer and a control gate (2018-08-14),
13. RE46526 - Non-volatile semiconductor storage device (2017-08-28),
14. 9691484 - Semiconductor memory device with memory cells each including a charge accumulation layer and a control gate (2017-06-27),
15. 9324432 - Semiconductor memory device with memory cells each including a charge accumulation layer and a control gate (2016-04-26),

Title: Inventor Dai Nakamura: Revolutionizing Technology in Kawasaki

Introduction: Dai Nakamura is a visionary inventor based in Kawasaki, Japan, known for his groundbreaking contributions to the field of technology and innovation.

Latest Patents: Dai Nakamura holds several patents in the areas of robotics, artificial intelligence, and renewable energy technologies, showcasing his commitment to pushing the boundaries of what is possible in the modern world.

Career Highlights: With a career spanning over two decades, Dai Nakamura has worked with leading tech companies and research institutions to develop cutting-edge solutions that have revolutionized industries and improved the lives of many.

Collaborations: Throughout his career, Dai Nakamura has collaborated with top engineers, scientists, and researchers from around the globe, fostering a culture of innovation and excellence in all his projects.

Conclusion: Dai Nakamura's relentless pursuit of innovation and his passion for creating a better future through technology make him a true pioneer in the world of inventions.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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