Hsinchu, Taiwan

Chunting Lee

This inventor holds 1 USPTO granted patent and 3 published patent applications. Top assignee: Taiwan Semiconductor Manufacturing Comp. Ltd.. Active years: 2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Chunting Lee. Retrieved from https://idiyas.com/inventor/chunting-lee

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 1 

Average Co-Inventor Count = 1.0

ph-index = 1


Company Filing History:


Years Active: 2026

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1 patent (USPTO):Explore Patents

Title: Chunting Lee and Advances in MOL Interconnect Technology.

Introduction

Chunting Lee is an inventor based in Hsinchu, Taiwan. His patent work includes a middle-of-line (MOL) interconnect design that uses molybdenum-containing structures to support semiconductor device connections.

Latest Patents

Lee is associated with 1 patent, titled “Molybdenum-Containing Device-Level Interconnects.” The patent describes MOL interconnect structures and techniques for forming them. Its design includes barrier-free source/drain contacts, source/drain vias, and gate vias within an insulator layer. The contacts and gate vias may contain tungsten, molybdenum, or both, while the source/drain vias include molybdenum. The patent also describes vias narrower than about 16 nanometers and the possibility of forming source/drain and gate vias together through a shared bottom-up deposition process.

Career Highlights

Lee is associated with Taiwan Semiconductor Manufacturing Company Limited. His patent focuses on materials and fabrication techniques for compact semiconductor interconnects.

Collaborations

The provided information identifies Hsiao Chu Chen and Wei-Hsuan Chen as Lee’s coworkers. Their names are associated with his professional context, though specific roles in the patent are not provided.

Conclusion

Chunting Lee’s patent addresses barrier-free, molybdenum-containing MOL interconnects and fabrication methods intended for semiconductor devices.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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