Hsinchu, Taiwan

Chung-Shih Chiang

This inventor holds 1 USPTO granted patent and 1 published patent application. Top assignee: Taiwan Semiconductor Manufacturing Comp. Ltd.. Active years: 2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Chung-Shih Chiang. Retrieved from https://idiyas.com/inventor/chung-shih-chiang

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 1 

Average Co-Inventor Count = 1.0

ph-index = 1


Company Filing History:


Years Active: 2026

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1 patent (USPTO):Explore Patents

Title: Chung-Shih Chiang and High-Voltage Device Innovation.

Introduction

Chung-Shih Chiang is an inventor associated with Hsinchu, Taiwan, and Taiwan Semiconductor Manufacturing Company Limited. His patent work addresses high-voltage semiconductor device structures and methods for forming them.

Latest Patents

Chiang is associated with 1 patent: “High Voltage Device Structure and Methods of Forming the Same.” The patent describes a structure with a deep well region and a doped region in a substrate, surrounded by a well region. It also includes source and drain regions, along with a pickup region that contacts the source laterally. The pickup, well, and deep well regions are electrically connected. This arrangement provides a structural approach to implementing a high-voltage device.

Career Highlights

Chiang’s listed invention concerns semiconductor device design and fabrication, an area relevant to the development of high-voltage components. His work is associated with Taiwan Semiconductor Manufacturing Company Limited, a semiconductor company based in Taiwan.

Collaborations

Chien-Ming Ku is identified as Chiang’s coworker. The available information does not specify a particular joint patent or project between them.

Conclusion

Chung-Shih Chiang’s patent reflects his contribution to high-voltage semiconductor device design through a structure that integrates connected well regions with source and drain components.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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