Hsinchu, Taiwan

Chun-Wei Hsu

This inventor holds 1 USPTO granted patent and 1 published patent application. Top assignee: Taiwan Semiconductor Manufacturing Co., Ltd.. Active years: 2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Chun-Wei Hsu. Retrieved from https://idiyas.com/inventor/chun-wei-hsu-d84n07mh

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 1 

Average Co-Inventor Count = 1.0


Company Filing History:


Years Active: 2026

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1 patent (USPTO):Explore Patents

Title: Chun-Wei Hsu: Semiconductor Process-Control Inventor.

Introduction

Chun-Wei Hsu is an inventor based in Hsinchu, Taiwan. His patent work concerns semiconductor manufacturing, particularly chemical mechanical planarization (CMP), a process used to smooth and flatten semiconductor wafers. Hsu is associated with Taiwan Semiconductor Manufacturing Co., Ltd.

Latest Patents

Hsu is named on 1 patent, titled “System and Method for Controlling Chemical Mechanical Planarization.” The invention describes a CMP system with a camera that captures an image of the planarization head after it unloads a wafer. A control system analyzes the image for damage. If damage is detected, the system prevents further CMP operations until the head is repaired; if no damage is found, it allows the head to receive another wafer. This approach is designed to identify equipment damage before the next processing cycle.

Career Highlights

Hsu’s patent reflects an emphasis on equipment monitoring and process control in semiconductor manufacturing. By using image analysis to check a CMP head between wafer-processing operations, the system can help prevent continued use of damaged equipment.

Collaborations

The patent is associated with Taiwan Semiconductor Manufacturing Co., Ltd., connecting Hsu’s invention to the company’s semiconductor manufacturing work.

Conclusion

Chun-Wei Hsu’s patented system applies camera-based inspection and automated control to CMP equipment, addressing damage detection between wafer-processing cycles.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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