Taoyuan, Taiwan

Chun-Hsien Wen

This inventor holds 1 USPTO granted patent and 2 published patent applications. Top assignee: Taiwan Semiconductor Manufacturing Comp. Ltd.. Active years: 2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Chun-Hsien Wen. Retrieved from https://idiyas.com/inventor/chun-hsien-wen-kljjzekc

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 1 

Average Co-Inventor Count = 1.0

ph-index = 1


Company Filing History:


Years Active: 2026

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1 patent (USPTO):Explore Patents

Title: Chun-Hsien Wen: Semiconductor Interconnect Invention

Introduction

Chun-Hsien Wen is an inventor associated with Taoyuan, Taiwan, and Taiwan Semiconductor Manufacturing Company Limited. His patent work concerns semiconductor connection structures designed to support electrical connections between vias.

Latest Patents

Wen is credited with 1 patent: “Via Connection Structure Having Multiple Via-to-Via Connections.” The invention describes a conductive structure positioned between and electrically contacting multiple via structures. The vias are laterally offset from neighboring vias rather than stacked, and conductive traces and footprints connect each via electrically to at least two other vias on the same device level.

Career Highlights

Wen’s listed patent reflects work on semiconductor interconnect design and manufacturing methods. Its laterally offset via arrangement provides an alternative to stacked-via connections within a semiconductor device.

Collaborations

Wen’s listed coworkers include Ting-Yu Yeh and Shu-Cheng Li. The patent is associated with Taiwan Semiconductor Manufacturing Company Limited.

Conclusion

Chun-Hsien Wen’s patent contribution focuses on a semiconductor connection structure that links multiple laterally offset vias through conductive features.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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