Choon-Hun Choo

Title: Choon-Hun Choo: Innovator in Clock Network Architecture

Introduction

Choon-Hun Choo is a notable inventor based in Perak, Malaysia. He has made significant contributions to the field of structured ASIC design, particularly in clock network architecture. His innovative work has led to the development of a unique clock architecture that enhances the performance of ASIC chips.

Latest Patents

Choo holds a patent for a "Clock network fishbone architecture for a structured ASIC manufactured on a 28 NM CMOS process lithographic node." This patent describes a clock architecture for a Structured ASIC chip, which is manufactured using a CMOS process. The architecture features a via-configurable logic block (VCLB) that includes a core region with memory and logic cells arranged in columns. The clock network consists of a global clock network tree and a low-level clock mesh that distributes the global clock signal in a repeating pattern. The fishbone configuration of the clock mesh allows for scalable expansion, providing up to 36 global clocks with four clocks per logic cell.

Career Highlights

Choon-Hun Choo is associated with Easic Corporation, where he applies his expertise in ASIC design and clock network architecture. His work has been instrumental in advancing the capabilities of structured ASICs, particularly in the context of modern CMOS processes.

Collaborations

Choo has collaborated with notable colleagues, including Andrey V Nikishin and Phey-Chuin Tan. These collaborations have contributed to the development of innovative solutions in the field of ASIC technology.

Conclusion

Choon-Hun Choo's contributions to clock network architecture exemplify the innovative spirit of modern inventors. His work continues to influence the design and functionality of structured ASICs, showcasing the importance of innovation in technology.