Medfield, MA, United States of America

Chirravuri Jagannath

This inventor holds 7 USPTO granted patents. Top assignee: Gte Laboratories Incorporated. Active years: 1991-1994.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Chirravuri Jagannath. Retrieved from https://idiyas.com/inventor/chirravuri-jagannath

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


% Patents Active = 100.0

Average Co-Inventor Count = 4.3

ph-index = 6

Forward Citations = 242(Granted Patents)


Location History:

  • Needham, MA (US) (1992 - 1993)
  • Medfield, MA (US) (1991 - 1994)

Company Filing History:


Years Active: 1991-1994

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7 patents (USPTO):Explore Patents

Title: Innovations of Chirravuri Jagannath

Introduction

Chirravuri Jagannath is a notable inventor based in Medfield, MA (US). He has made significant contributions to the field of semiconductor technology, holding a total of seven patents. His work focuses on advanced methods of fabricating semiconductor structures that address critical challenges in the industry.

Latest Patents

One of his latest patents is titled "Method of fabricating highly lattice mismatched quantum well structures." This innovative method involves the growth of a quantum well active region that is highly lattice-mismatched relative to a substrate. The process includes the growth of a buffer layer that relieves stress through the formation of misfit dislocations. Additionally, a strained superlattice structure is grown to terminate any upwardly-propagating dislocations, followed by the growth of an unstrained barrier layer. The final step involves the growth of a quantum well structure that minimizes the lattice constant mismatch, ensuring efficient stress accommodation.

Another significant patent is the "Method of manufacturing a heteroepitaxial semiconductor structure." This patent describes the fabrication of heteroepitaxial semiconductor structures, such as GaAs on InP or Si. The GaAs is grown in the form of individual spaced-apart islands, which minimizes stress due to thermal expansion mismatches. This innovative approach allows for the effective production of high-quality semiconductor materials.

Career Highlights

Chirravuri Jagannath is currently employed at GTE Laboratories Incorporated, where he continues to advance semiconductor technology. His expertise in fabricating complex semiconductor structures has positioned him as a key figure in the field.

Collaborations

Throughout his career, Jagannath has collaborated with esteemed colleagues, including Boris S. Elman and Craig A. Armiento. These collaborations have further enriched his research and development efforts in semiconductor innovations.

Conclusion

Chirravuri Jagannath's contributions to semiconductor technology through his innovative patents demonstrate his significant impact on the field. His work continues to influence advancements in the industry, showcasing the importance of innovation in technology.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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