Hsinchu, Taiwan

Ching-Wei Lin

This inventor holds 1 USPTO granted patent and 2 published patent applications. Top assignee: Taiwan Semiconductor Manufacturing Comp. Ltd.. Active years: 2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Ching-Wei Lin. Retrieved from https://idiyas.com/inventor/ching-wei-lin-536sg58i

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 1 

Average Co-Inventor Count = 1.0

ph-index = 1


Company Filing History:


Years Active: 2026

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1 patent (USPTO):Explore Patents

Title: Ching-Wei Lin: Innovator in Semiconductor Technology

Introduction

Ching-Wei Lin is a talented inventor based in Hsinchu, Taiwan. She has made significant contributions to the field of semiconductor technology. Although she currently holds no granted patents, her innovative ideas are reflected in her latest patent applications.

Latest Patent Applications

Ching-Wei Lin's recent patent applications include a "Semiconductor Package Redistribution Structure and Fabrication Method Thereof." This application describes a semiconductor device that features an interconnect structure over a substrate and a redistribution layer above it. The redistribution layer consists of a first via, a first metal line, a second via, and a second metal line. Notably, the width of the first metal line is greater than that of the second metal line, while their thicknesses are equal. Each metal line has a top portion with a conductive material of a first grain size and a bottom portion with a second grain size, where the first grain size is larger than the second.

Another application is for a "Low-Stress Passivation Layer." This application outlines methods for forming semiconductor devices. The process begins with a workpiece that has a redistribution layer electrically coupled to an interconnect structure. The method includes patterning the redistribution layer to create a recess that separates two conductive features. A first dielectric layer is deposited over these features and within the recess, followed by a nitride layer. Portions of the nitride layer over the corners of the conductive features are then removed.

Conclusion

Ching-Wei Lin is an innovative inventor whose work in semiconductor technology showcases her potential in the field. Her latest patent applications reflect her commitment to advancing semiconductor device design and fabrication methods.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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