Eindhoven, Netherlands

Ching-lun Lee

This inventor holds 1 USPTO granted patent. Top assignee: Ams-Osram Ag. Active years: 2025.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Ching-lun Lee. Retrieved from https://idiyas.com/inventor/ching-lun-lee-rrlnf58b

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


% Patents Active = 100.0

Average Co-Inventor Count = 1.0

ph-index = 1


Company Filing History:


Years Active: 2025

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1 patent (USPTO):Explore Patents

Title: Innovations of Ching-lun Lee in Semiconductor Technology

Introduction

Ching-lun Lee is a notable inventor based in Eindhoven, Netherlands. He has made significant contributions to the field of semiconductor technology, particularly through his innovative patent.

Latest Patents

Ching-lun Lee holds a patent for a "Semiconductor device with a bond pad and a sandwich passivation layer and manufacturing method thereof." This patent describes a method of forming a sandwich passivation layer on a semiconductor device that includes a bond pad. The method involves forming a first layer over the surface of the semiconductor device, removing a part of the first layer to expose the bond pad, forming a second layer over both the first layer and the bond pad, and finally forming a third layer over the second layer. Notably, the surface of the bond pad remains uncontacted by the first and third layers. He has 1 patent to his name.

Career Highlights

Ching-lun Lee is currently associated with ams OSRAM AG, a company known for its advancements in sensor solutions and lighting technologies. His work at the company focuses on enhancing semiconductor devices, which are crucial for various electronic applications.

Collaborations

Due to space constraints, the collaborations section will be omitted.

Conclusion

Ching-lun Lee's contributions to semiconductor technology through his innovative patent demonstrate his expertise and commitment to advancing the field. His work continues to influence the development of efficient semiconductor devices.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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