Hsinchu, Taiwan

Chin-Yang Wu

This inventor holds 1 USPTO granted patent. Top assignee: Taiwan Semiconductor Manufacturing Comp. Ltd.. Active years: 2019.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Chin-Yang Wu. Retrieved from https://idiyas.com/inventor/chin-yang-wu-mgtlajaw

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank

% Patents Active = 100.0

Average Co-Inventor Count = 4.0

ph-index = 1

Forward Citations = 2(Granted Patents)


Company Filing History:


Years Active: 2019

Loading Chart...
1 patent (USPTO):Explore Patents

Title: Chin-Yang Wu and His Patent in Phase-Locked Loop Technology.

Introduction

Chin-Yang Wu is an inventor based in Hsinchu, Taiwan. His listed patent work is associated with Taiwan Semiconductor Manufacturing Company Limited, and his portfolio includes 1 patent.

Latest Patents

Wu’s patent, “Injection-Locked Digital Bang-Bang Phase-Locked Loop with Timing Calibration,” describes a phase-locked loop circuit designed to calibrate injection timing and optimize bandwidth. The circuit combines a digital bang-bang phase-locked loop with a down-sampling circuit, a digitally controlled delay line, an injection pulser, and an injection timing calibration circuit. By adjusting the timing of the injection pulse, the design aims to reduce jitter in the PLL’s output signal.

Career Highlights

The available information connects Wu’s patent activity with Taiwan Semiconductor Manufacturing Company Limited. His disclosed invention addresses timing calibration and jitter reduction in digital phase-locked loop circuitry.

Collaborations

Wu’s listed coworkers include Ruey-Bin Sheen and Chih-Hsien Chang. Their names are associated with the provided information about his professional and patent context.

Conclusion

Chin-Yang Wu’s patent presents a timing-calibration approach for injection-locked digital phase-locked loops, with the goal of improving bandwidth optimization and reducing output jitter.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
Loading…