Chin-Wei Jim Chang

Title: Innovations by Chin-Wei Jim Chang

Introduction

Chin-Wei Jim Chang is a notable inventor based in Fremont, CA. He has made significant contributions to the field of static timing analysis, particularly in the context of System on a Chip (SoC) designs. His innovative approach addresses longstanding challenges in timing analysis, making it more efficient and accessible.

Latest Patents

Chin-Wei Jim Chang holds a patent for a "Method and system for high speed and low memory footprint static timing analysis." This invention provides a method and system for performing Static Timing Analysis on SoC designs. It solves a longstanding problem with timing analysis of designs, namely, the ability to multi-thread the design under analysis. The invention allows for slicing a design into levels, further decomposing each level into gates, and the multi-threaded processing of gates. This results in significantly faster solutions for large design analysis compared to current approaches. Additionally, the invention ensures that only one level exists in the RAM at any time. Once the arrival time on the level is computed, the data is saved to disk immediately. Because the memory footprint is sub-linear to the size of the design, entire system-on-a-chip designs may be run on inexpensive, off-the-shelf hardware. He has 1 patent to his name.

Career Highlights

Chin-Wei Jim Chang is currently employed at Synopsys, Inc., a leading company in electronic design automation. His work at Synopsys has allowed him to further develop his innovative ideas and contribute to advancements in the field of semiconductor design.

Collaborations

Chin-Wei has collaborated with notable colleagues such as Yuji Kukimoto and Haobin Li. Their teamwork has fostered an environment of innovation and creativity, leading to significant advancements in their projects.

Conclusion

Chin-Wei Jim Chang's contributions to static timing analysis represent a significant advancement in the field of semiconductor design. His innovative methods not only enhance efficiency but also reduce costs, making high-performance designs more accessible.