Hyogo, Japan

Chikako Nakanishi

This inventor holds 3 USPTO granted patents. Top assignee: Mitsubishi Denki Kabushiki Kaisha. Active years: 1998-1999.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Chikako Nakanishi. Retrieved from https://idiyas.com/inventor/chikako-nakanishi

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


% Patents Active = 100.0

Average Co-Inventor Count = 1.2

ph-index = 3

Forward Citations = 45(Granted Patents)


Location History:

  • Tokyo, JP (1998)
  • Hyogo, JP (1998 - 1999)

Company Filing History:


Years Active: 1998-1999

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3 patents (USPTO):Explore Patents

Title: Chikako Nakanishi: Innovator in Instruction Cache Memory Technology

Introduction

Chikako Nakanishi is a prominent inventor based in Hyogo, Japan. She has made significant contributions to the field of computer engineering, particularly in the development of advanced instruction cache memory systems. With a total of 3 patents to her name, Nakanishi's work has had a substantial impact on improving the efficiency and reliability of processing systems.

Latest Patents

Nakanishi's latest patents include an innovative instruction cache memory apparatus with an advanced read function. This invention provides a low probability of occurrence of cache errors. The instruction cache memory features an advanced read function that allows for the provision and reception of instruction information in block units to and from a main memory. It includes an instruction analysis section that predicts the necessity of reading the next block from the main memory by analyzing the instructions currently being transferred to the instruction cache. Additionally, circuits are in place to read out the next block from the main memory when deemed necessary by the instruction analysis section.

Another notable patent is her branch prediction system for superscalar processors. This system utilizes branch target buffers (BTBs) that store branch prediction information on branch instructions, including a 2-bit offset indicating the location of the branch instruction within a cache block. The BTBs simultaneously output branch prediction information based on an executable instruction address, allowing for more efficient processing.

Career Highlights

Chikako Nakanishi is currently employed at Mitsubishi Electric Corporation, where she continues to innovate in the field of computer technology. Her work has been recognized for its technical depth and practical applications in enhancing processing capabilities.

Collaborations

Nakanishi collaborates with her coworker, Hideki Ando, contributing to various projects that aim to advance technology in their field.

Conclusion

Chikako Nakanishi's contributions to instruction cache memory technology exemplify her role as a leading inventor in the field. Her innovative patents reflect her commitment to enhancing computer processing systems, making her a significant figure in the world of technology.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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