Mitsubishi Denki Kabushiki Kaisha

Chikako Nakanishi

Hideki Ando

An instruction cache memory provides a low probability of occurrence of cache error. The instruction cache memory includes an advance read function with an instruction cache for providing/receiving instruction formation in block unit to/from a main memory, an instruction analysis section for predicting whether it is necessary to read out a next block from the main memory by analyzing the instructions included in the block read out from the main memory presently being transferred to the instruction cache, and circuits for reading out the next block from the main memory to transfer to the instruction cache when predicted to be necessary by the instruction analysis section. Prediction is done by judging if a branch predict signal produced within the instruction cache memory is present or not, judging the branch destination to be within the block or in the next block when the branch instruction is detected, and judging whether the branch operation is a forward branch or a backward branch.

Instruction cache memory apparatus with advanced read function that

Each entry of BTBs (11 and 21) stores branch prediction information on a branch instruction including a 2-bit offset which indicates a location at which the branch instruction is stored in a cache block. The BTBs (11 and 21) simultaneously output the branch prediction informations stored in the entries specified by an index of an executable instruction address in an address fetch unit (1) as the first and second retrieval branch prediction informations, respectively. A selection circuit (2) determines a next program counter value (PC') on the basis of outputs of tag detection circuits (12 and 22), outputs of PC detection circuits (13 and 23), a tag in the address fetch unit (1), a program counter value (PC) and the first and second retrieval branch prediction informations.

Branch prediction system for superscalar processor

A bypass control circuit uses a plurality of entries corresponding to a plurality of addresses of a register file to grasp in which one of eight result buffers a processing result of an instruction having a destination address corresponding to any of the plurality of entries exists. When a source address of data to be required by a latch circuit matches with a destination address of a processing result of an instruction held in any of the eight result buffers, the processing result of the instruction having the matching destination address is transferred from a result buffer holding the processing result of the instruction to the latch circuit. Thus, fast bypass control can be achieved.

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Hyogo, Japan

Chikako Nakanishi