Chih-kuo Yu

Title: The Innovations of Chih-kuo Yu

Introduction

Chih-kuo Yu is a notable inventor based in San Jose, California. He has made significant contributions to the field of electronic design automation. His work focuses on improving the efficiency of gate level simulations.

Latest Patents

Chih-kuo Yu holds a patent for a "System and method for generating reduced standard delay format files for gate level simulation." This innovative system and method disclose a process for generating standard delay format (SDF) files. For each timing closed hierarchical instance, timing arcs on internal register to register paths may be marked as zero delay arcs. If the zero delay causes a hold violation, an adjustment may be computed to fix the violation. If the adjustment does not cause a setup violation, the adjustment may be applied to the end point register.

Career Highlights

Chih-kuo Yu is currently employed at Cadence Design Systems, Inc. His role at the company allows him to leverage his expertise in electronic design automation. He has been instrumental in developing solutions that enhance simulation accuracy and efficiency.

Collaborations

Chih-kuo Yu has collaborated with talented individuals such as Akash Khandelwal and Pawan Kulshreshtha. These collaborations have contributed to the advancement of innovative technologies in the field.

Conclusion

Chih-kuo Yu's contributions to electronic design automation through his patent and work at Cadence Design Systems, Inc. highlight his importance as an inventor. His innovative approaches continue to shape the future of gate level simulations.