Cadence Design Systems, Inc.

Chih-kuo Yu

Rajarshi Mukherjee

Pawan Kulshreshtha

Akash Khandelwal

A system and method for generating standard delay format (SDF) files is disclosed. For each timing closed hierarchical instance, timing arcs on internal register to register paths may be marked as zero delay arcs. If the zero delay causes a hold violation, an adjustment may be computed to fix the violation. If the adjustment does not cause a setup violation, the adjustment may be applied to the end point register.

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San Jose, CA, United States of America

Chih-kuo Yu