This inventor holds 1 USPTO granted patent. Top assignee: Taiwan Semiconductor Manufacturing Co., Ltd.. Active years: 2026.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile
Company Filing History:
Years Active: 2026
Title: Chih-Hsiung Peng: Semiconductor Device Innovation
Introduction
Chih-Hsiung Peng is an inventor based in Hsinchu, Taiwan. His patent work concerns semiconductor device fabrication, including transistor structures and methods for forming electrical isolation. Peng is associated with Taiwan Semiconductor Manufacturing Co., Ltd. (TSMC).
Latest Patents
Peng is named on 1 patent: “Field Effect Transistor with Isolation Structure and Related Method.” The invention describes forming two adjacent stacks of semiconductor channels over a substrate, with a transition region where their protruding corners meet. Sacrificial gates are formed over the stacks, alongside a wider bar structure over the transition region.
The method then forms source/drain openings and regions in areas exposed by the gates and bar structure. The sacrificial gates are replaced with gate structures that wrap around the semiconductor channels. The bar structure is replaced with an inactive gate structure, which is subsequently replaced by an isolation structure. This process provides a way to integrate isolation into a transistor layout while forming gate and source/drain features.
Career Highlights
Peng’s listed patent reflects work on advanced transistor architecture and semiconductor manufacturing processes. Its focus on channel stacks, wraparound gates, and isolation structures addresses the design and fabrication of closely arranged semiconductor devices.
Collaborations
The patent lists Shih-Chi Fu and Kuei-Shun Chen as Peng’s coworkers. Their shared work is associated with TSMC and the development of the described transistor and isolation method.
Conclusion
Chih-Hsiung Peng’s patent documents a semiconductor fabrication approach that combines stacked channels, wraparound gate structures, and an integrated isolation feature.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile