Field effect transistor with isolation structure and related method

Abstract

A method includes: forming a first stack of semiconductor channels and a second stack of semiconductor channels over a substrate, the first stack being adjacent the second stack, a transition region overlapping neighboring protruding corners of the first stack and the second stack; forming a plurality of sacrificial gates over the first stack and the second stack, the plurality of sacrificial gates extending in a first direction and being arranged along a second direction transverse the first direction based on a first pitch along a second direction, each of the plurality of sacrificial gates having a first width; simultaneously with the forming a plurality of sacrificial gates, forming a bar structure over the transition region and adjacent to the plurality of sacrificial gates, the bar structure having a second width that exceeds a sum of the first pitch and the first width; forming a plurality of source/drain openings in areas of the first and second stacks of semiconductor channels that are exposed by the plurality of sacrificial gates and the bar structure; forming a plurality of source/drain regions in the plurality of source/drain openings; replacing the plurality of sacrificial gates with a plurality of gate structures that wrap around the semiconductor channels of the first and second stacks; simultaneously with replacing the plurality of sacrificial gates, replacing the bar structure with an inactive gate structure; and replacing the inactive gate structure with an isolation structure.