Hsinchu, Taiwan

Chih-Houng Chou

This inventor holds 1 USPTO granted patent. Top assignee: United Microelectronics Corp.. Active years: 2000.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Chih-Houng Chou. Retrieved from https://idiyas.com/inventor/chih-houng-chou

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank

% Patents Active = 100.0

Average Co-Inventor Count = 4.0

ph-index = 1

Forward Citations = 6(Granted Patents)


Company Filing History:


Years Active: 2000

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1 patent (USPTO):Explore Patents

Title: Chih-Houng Chou: Plasma-Etching Protection for Wafer Clamps.

Introduction

Chih-Houng Chou is an inventor associated with Hsinchu, Taiwan, and United Microelectronics Corporation. His patent work addresses protecting wafer-clamp components from plasma etching during semiconductor processing.

Latest Patents

The provided information lists one patent for Chou: “Apparatus for Preventing Plasma Etching of a Wafer Clamp.” The invention describes an apparatus used in a process chamber, with components including a pedestal, electrodes, a wafer clamp, a semiconductor wafer, a quartz ring, a cooling plate, an anodized surface, and a gas hole.

The wafer clamp secures the semiconductor wafer and includes a clamp ring, a concave holder, and a depression. The clamp ring supports the wafer, while the concave holder has a semi-elliptical surface and polymer on its backside to help prevent plasma etching during deposition or etching. The depression is positioned higher and adjacent to the concave holder.

Career Highlights

Chou’s listed patent reflects work on equipment design for semiconductor manufacturing. Its focus is protecting the wafer clamp from plasma exposure during processing.

Collaborations

Chung-Chien Lu and Gary Lin are identified as Chou’s coworkers. The provided information does not specify their roles in the patent or the extent of their collaboration.

Conclusion

Chih-Houng Chou’s listed invention addresses a practical challenge in semiconductor processing by designing a wafer clamp intended to resist plasma etching.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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