Chien-Hsiung Peng

Title: Chien-Hsiung Peng: Innovator in Wafer Acceptance Testing

Introduction

Chien-Hsiung Peng is a notable inventor based in Santa Clara, CA. He has made significant contributions to the field of semiconductor technology, particularly in the area of wafer acceptance testing. His innovative work has led to the development of a patented system that enhances yield forecasting in semiconductor manufacturing.

Latest Patents

Chien-Hsiung Peng holds a patent for a "System and method for generating a yield forecast based on wafer acceptance tests." This patent describes a comprehensive WAT system that includes several subsystems. The saturation current WAT subsystem generates a weighted standard deviation based on target NMOS and PMOS saturation currents. The wafer IC speed WAT subsystem produces a speed performance probability distribution based on the weighted standard deviation and speed WAT results. Additionally, the wafer IC power WAT subsystem utilizes speed and power WAT results to create a power performance model. Finally, the yield calculator generates a yield forecast based on the power performance model and variance probability distributions.

Career Highlights

Chien-Hsiung Peng is currently employed at Nvidia Corporation, a leading company in graphics processing technology. His work at Nvidia has allowed him to collaborate with other talented professionals in the field. His contributions have been instrumental in advancing the company's capabilities in semiconductor technology.

Collaborations

Chien-Hsiung Peng has worked alongside notable colleagues such as Craig Nishizaki and Peter Hung. Their collaborative efforts have further enhanced the innovative projects at Nvidia Corporation.

Conclusion

Chien-Hsiung Peng is a distinguished inventor whose work in wafer acceptance testing has made a significant impact on the semiconductor industry. His patented system for yield forecasting exemplifies his commitment to innovation and excellence in technology.