The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 08, 2015
Filed:
Oct. 30, 2012
Nvidia Corporation, Santa Clara, CA (US);
Craig Nishizaki, Santa Clara, CA (US);
Peter Hung, Santa Clara, CA (US);
Gunaseelan Ponnuvel, Santa Clara, CA (US);
Chien-Hsiung Peng, Santa Clara, CA (US);
NVIDIA CORPORATION, Santa Clara, CA (US);
Abstract
A wafer acceptance test (WAT) system and method that, in one embodiment, includes: (1) a saturation current WAT subsystem operable to generate a weighted standard deviation based on target NMOS and PMOS saturation currents and saturation current WAT results, (2) a wafer IC speed WAT subsystem operable to generate a speed performance probability distribution of wafer ICs based on the weighted standard deviation and speed WAT results, (3) a wafer IC power WAT subsystem operable to employ the speed WAT results and power WAT results to generate a power performance model of wafer ICs, and (4) a yield calculator operable to generate a power performance variance probability distribution of wafer ICs based on the power performance model and the power WAT results, and to employ the speed performance probability distribution and the power performance variance probability distribution to generate the yield forecast with respect to a target performance profile.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile