Taipei, Taiwan

Chien-Fu Tseng

This inventor holds 1 USPTO granted patent and 6 published patent applications. Top assignee: Taiwan Semiconductor Manufacturing Co., Ltd.. Active years: 2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Chien-Fu Tseng. Retrieved from https://idiyas.com/inventor/chien-fu-tseng-ngo95ae6

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 1 

Average Co-Inventor Count = 1.0

ph-index = 1


Company Filing History:


Years Active: 2026

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1 patent (USPTO):Explore Patents

Title: Chien-Fu Tseng and Semiconductor Packaging Innovation.

Introduction

Chien-Fu Tseng is an inventor associated with Taipei, Taiwan, and Taiwan Semiconductor Manufacturing Co., Ltd. His patent work addresses semiconductor packaging methods designed to improve manufacturing flexibility and efficiency.

Latest Patents

Tseng is named on one patent: “Methods of Forming Packages and Resulting Structures.” The invention describes forming redistribution-layer (RDL) contact features aligned with through-silicon vias (TSVs), even when their critical dimensions differ because of separate manufacturing processes. It also presents methods for exposing underlying TSVs through self-aligned techniques without requiring additional photolithography steps.

Career Highlights

Tseng’s documented patent contribution focuses on semiconductor packaging and the alignment of RDL contacts with TSVs. The approach is intended to accommodate process variation while supporting efficient package fabrication.

Collaborations

Tseng’s listed coworker is Yu Chieh Yung. Their shared association with the patent reflects collaborative work on methods for forming semiconductor packages and related structures.

Conclusion

Chien-Fu Tseng’s patent highlights practical approaches to improving alignment and manufacturing flexibility in semiconductor packaging.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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