Hsinchu, Taiwan

Chia-wei Huang

This inventor holds 1 USPTO granted patent and 1 published patent application. Top assignee: Taiwan Semiconductor Manufacturing Comp. Ltd.. Active years: 2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Chia-wei Huang. Retrieved from https://idiyas.com/inventor/chia-wei-huang-ho9ss4ps

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 1 

Average Co-Inventor Count = 1.0

ph-index = 1


Company Filing History:


Years Active: 2026

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1 patent (USPTO):Explore Patents

Title: Chia-wei Huang and Semiconductor Test-Circuit Innovation.

Introduction

Chia-wei Huang is an inventor associated with Hsinchu, Taiwan, and Taiwan Semiconductor Manufacturing Company Limited. His patent work concerns wafer-level testing circuitry for semiconductor devices.

Latest Patents

The provided information identifies one patent for Huang: “Test Circuit and Method for Operating the Same.” The patent describes a wafer with a die, an adjacent scribe line, and a test circuit positioned beside the scribe line. The circuit uses switches to connect two devices under test, arranged in separate columns, to signal supply and receive nodes. Its configuration allows both devices to be coupled simultaneously, with no switch connected between them. This arrangement addresses how test signals are applied to and received from devices during wafer testing.

Career Highlights

Huang’s listed patent reflects work on semiconductor testing and circuit design. The disclosed approach focuses on coordinating signal connections for multiple devices under test on a wafer. The supplied information attributes 1 patent to him.

Collaborations

Wei-Jhih Wang and Cheng-Cheng Kuo are identified as Huang’s coworkers. The available details do not specify their roles in the patent or describe particular collaborative projects.

Conclusion

Chia-wei Huang’s documented invention concerns a wafer test circuit designed to connect multiple devices under test efficiently, highlighting his contribution to semiconductor testing technology.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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