This inventor holds 2 USPTO granted patents. Top assignee: Holtek Microelectronics Inc.. Active years: 1998-1999.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile
Company Filing History:
Years Active: 1998-1999
Title: Chia Chen Liu: Innovator in Semiconductor Fabrication
Introduction
Chia Chen Liu is a prominent inventor based in Hsinchu, Taiwan. He has made significant contributions to the field of semiconductor fabrication, holding 2 patents that showcase his innovative approaches to integrated circuit design.
Latest Patents
Liu's latest patents include a method titled "Modified zero layer align method of twin well MOS fabrication." This invention discloses a technique for fabricating alignment marks in a twin-well integrated circuit without the need for a zero-layer photomask. The method involves several steps, including forming a pad oxide layer on a P-type semiconductor wafer and using a photolithography technique to expose alignment mark patterns. Another notable patent is "Nitride double etching for twin well align," which outlines a process for fabricating alignment marks on an integrated circuit device. This method includes forming a first pad oxide layer and first nitride layer, followed by ion implantation to create N-doped and P-doped regions.
Career Highlights
Chia Chen Liu is currently employed at Holtek Microelectronics Inc., where he continues to develop innovative solutions in semiconductor technology. His work has significantly impacted the efficiency and precision of integrated circuit fabrication.
Collaborations
Liu collaborates with Chwan Chao Chen, contributing to advancements in their field through shared expertise and innovative ideas.
Conclusion
Chia Chen Liu's contributions to semiconductor fabrication through his patents and work at Holtek Microelectronics Inc. highlight his role as a key innovator in the industry. His methods are paving the way for more efficient integrated circuit designs.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile