The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 02, 1999
Filed:
Oct. 28, 1996
Chia Chen Liu, Hsinchu, TW;
Holtek Microelectonics, Inc., Hsinchu, TW;
Abstract
A method for fabricating alignment marks in a twin-well integrated circuit without using a zero-layer photomask is disclosed. This method involves the steps of: (a) forming a pad oxide layer on a P-type semiconductor wafer; (b) obtaining an N-well photomask containing an N-well pattern for defining an N-well region in the P-type semiconductor wafer and an alignment mark pattern for defining a plurality of alignment marks in the P-type semiconductor wafer, the N-well photomask is designed such that the alignment mark pattern and the N-well pattern can be separately exposed; (c) using a photolithography technique to expose only the alignment mark pattern to form a plurality of the alignment marks in the pad oxide layer and the P-type semiconductor wafer; (d) coating a first photoresist layer overlaying the pad oxide layer which is aligned using the alignment marks formed in step (b); (e) using the N-well photomask to pattern the first photoresist layer and define the N-well region; and (f) ion-implanting N-type impurities to form the N-well region in the P-type semiconductor wafer.