Leuven, Belgium

Chi Lim Tan

This inventor holds 1 USPTO granted patent. Top assignee: Imec Vzw. Active years: 2018.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Chi Lim Tan. Retrieved from https://idiyas.com/inventor/chi-lim-tan

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank

Average Co-Inventor Count = 2.0

ph-index = 1

Forward Citations = 1(Granted Patents)


Company Filing History:


Years Active: 2018

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1 patent (USPTO):Explore Patents

Title: Chi Lim Tan and Vertical Three-Dimensional Semiconductor Technology.

Introduction

Chi Lim Tan is an inventor based in Leuven, Belgium. His patent work concerns semiconductor device architecture and manufacturing, including vertical three-dimensional structures.

Latest Patents

Tan is associated with 1 patent: “Vertical Three-Dimensional Semiconductor Device and Method of Making Same.” The disclosed technology describes a source layer formed over a substrate and a horizontal stack of alternating electrically isolating layers and conductive gate layers above it. A vertical channel passes through the stack, with a drain positioned above the stack and channel. The source injects charge carriers into the channel, while the drain extracts them. Applying an electrical bias to at least one conductive gate layer changes the channel’s conductivity.

Career Highlights

Tan is associated with imec Vzw, a research and innovation organization based in Leuven. His patent reflects work on vertical semiconductor structures and methods for manufacturing them.

Collaborations

Tan’s listed coworker is Judit Gloria Lisoni Reyes. Their association provides context for the collaborative environment connected with his semiconductor work.

Conclusion

Chi Lim Tan’s patent describes a vertical three-dimensional semiconductor device that uses a layered gate structure to control charge flow through a vertical channel.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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