Imec Vzw

Chi Lim Tan

Judit Gloria Lisoni Reyes

The disclosed technology generally relates to semiconductor devices, and more particularly to a vertical three-dimensional semiconductor device and a method for manufacturing such a device. In one aspect, the vertical three-dimensional semiconductor device has a source layer formed over a substrate. A horizontal stack of alternating electrically isolating layers and electrically conductive gate layers are formed over the source layer, wherein one of the electrically isolating layers contacts the source layer. A vertical channel structure extends vertically through the horizontal stack of alternating layers. A drain is formed over the horizontal stack of alternating layers and over the vertical channel structure. The source layer is configured to inject charge carriers into the vertical channel structure, and the metal drain is configured to extract charge carriers from the vertical channel structure. A conductivity of the vertical channel structure is configured to change in response to an electrical bias applied to at least one of the electrically conductive gate layers.

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Leuven, Belgium

Chi Lim Tan