IDiyas

For the Inventor, By the Inventor

San Jose, CA, United States of America

Cheng Qian

USPTO Granted Patents = 7

Average Co-Inventor Count = 2.3

ph-index = 3

Forward Citations = 37(Granted Patents)


Location History:

  • Santa Clara, CA (US) (2000)
  • San Jose, CA (US) (2004 - 2011)

Company Filing History:

goldMedal4 out of 2,353 
 
Lsi Corporation
 patents
silverMedal3 out of 3,715 
 
Lsi Logic Corporation
 patents

Years Active: 2000-2011

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7 patents (USPTO):Explore Patents
1. 7962833 - Unified memory architecture for recording applications (2011-06-14),
2. 7843366 - DVD EFM modulation architecture using two passes to reduce circuit size (2010-11-30),
3. 7624330 - Unified memory architecture for recording applications (2009-11-24),
4. 7600177 - Delta syndrome based iterative Reed-Solomon product code decoder (2009-10-06),
5. 6871316 - Delay reduction of hardware implementation of the maximum a posteriori (MAP) method (2005-03-22),
6. 6714606 - Integrated services digital broadcasting deinterleaver architecture (2004-03-30),
7. 6138265 - Decoding trellis coded modulated data with a conventional Viterbi decoder (2000-10-24),
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