The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 22, 2005

Filed:

Jan. 30, 2002
Applicants:

Alfred Kwok-kit Wong, Pokfulam, HK;

Cheng Qian, San Jose, CA (US);

Inventors:

Alfred Kwok-Kit Wong, Pokfulam, HK;

Cheng Qian, San Jose, CA (US);

Assignee:

LSI Logic Corporation, Milpitas, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M013/00 ;
U.S. Cl.
CPC ...
Abstract

A decoder generally comprising a branch metrics circuit and a state metrics circuit. The branch metrics circuit may be configured to generate a plurality of branch metric signals. The state metrics circuit may be configured to (i) add the branch metric signals to a plurality of state metric signals to generate a plurality of intermediate signals, (ii) determine a next state metric signal to the state metric signals, (iii) determine a normalization signal in response to the intermediate signals, and (iv) normalize the state metric signals in response to the normalization signal.


Find Patent Forward Citations

Wong, Alfred Kwok-Kit. (2005). Delay reduction of hardware implementation of the maximum a posteriori (map) method (U.S. Patent No. 6871316). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6871316

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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