New Taipei, Taiwan

Cheng-Hsiang Wu

This inventor holds 1 USPTO granted patent and 1 published patent application. Top assignee: Taiwan Semiconductor Manufacturing Comp. Ltd.. Active years: 2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Cheng-Hsiang Wu. Retrieved from https://idiyas.com/inventor/cheng-hsiang-wu-rh0h8hng

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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USPTO Granted Patents = 1 

Average Co-Inventor Count = 1.0

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Company Filing History:


Years Active: 2026

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1 patent (USPTO):Explore Patents

Title: Cheng-Hsiang Wu: Innovator in Semiconductor Structures

Introduction

Cheng-Hsiang Wu is an inventor based in New Taipei City, Taiwan. He has made significant contributions to the field of semiconductor technology. His work focuses on improving semiconductor structures and fabrication methods.

Latest Patent Applications

Cheng-Hsiang Wu has several notable patent applications. One of his latest applications is titled "SEMICONDUCTOR STRUCTURES WITH IMPROVED METAL CAPPING LAYERS." This application describes a method that includes forming a first dielectric layer on a semiconductor structure, which consists of a substrate and a multi-layer interconnect (MLI) structure. The method further details the formation of a through-substrate-via (TSV) opening and the subsequent processes to create multiple first metal vias and lines. Another application is "SEMICONDUCTOR STRUCTURES WITH COVER LAYERS." This application outlines a semiconductor structure that includes a die with a test pad featuring a probe mark. The application describes the layering of different materials to enhance the functionality of the semiconductor structure.

Conclusion

Cheng-Hsiang Wu is an innovative inventor whose work in semiconductor structures showcases his expertise in the field. His latest patent applications reflect his commitment to advancing semiconductor technology.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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