Taoyuan, Taiwan

Chen Yu Wu

This inventor holds 1 USPTO granted patent and 2 published patent applications. Top assignee: Taiwan Semiconductor Manufacturing Comp. Ltd.. Active years: 2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Chen Yu Wu. Retrieved from https://idiyas.com/inventor/chen-yu-wu-pgcsje8h

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 1 

Average Co-Inventor Count = 1.0

ph-index = 1


Company Filing History:


Years Active: 2026

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1 patent (USPTO):Explore Patents

Title: Chen Yu Wu: Integrated Circuit Packaging Inventor

Introduction

Chen Yu Wu is an inventor based in Taoyuan, Taiwan. His patent work includes methods for forming integrated circuit packages, with a focus on dielectric layers, metallization patterns, and wafer processing.

Latest Patents

Wu is associated with 1 patent: “Integrated Circuit Packages and Methods of Forming the Same.” The disclosed method deposits a first dielectric layer over both the package and scribe line regions of a wafer, then forms a first metallization pattern along and through that layer. A second dielectric layer is deposited over the first layer and metallization pattern. The second layer is then removed from the scribe line region while remaining in the package region. A second metallization pattern is formed along and through the remaining second dielectric layer, after which the wafer and first dielectric layer are sawed in the scribe line region.

Career Highlights

Wu is associated with Taiwan Semiconductor Manufacturing Co., Ltd. His patent describes a packaging process that distinguishes between the package and scribe line regions during layer deposition, pattern formation, and wafer sawing.

Collaborations

Wu’s listed coworkers include Wei-An Tsao and Po-Han Wang.

Conclusion

Chen Yu Wu’s patent work addresses integrated circuit package formation through coordinated dielectric-layer and metallization processing, followed by wafer sawing.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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