Shanghai, China

Chen Du

This inventor holds 1 USPTO granted patent. Top assignee: International Business Machines Corporation. Active years: 2014.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Chen Du. Retrieved from https://idiyas.com/inventor/chen-du-ecnq9i78

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


% Patents Active = 100.0

Average Co-Inventor Count = 4.0

ph-index = 1

Forward Citations = 6(Granted Patents)


Company Filing History:


Years Active: 2014

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1 patent (USPTO):Explore Patents

Title: Chen Du: Innovator in Chip Design

Introduction

Chen Du is a prominent inventor based in Shanghai, China. He has made significant contributions to the field of chip design, particularly in improving timing closure. His innovative approach has garnered attention in the technology sector.

Latest Patents

Chen Du holds a patent for a method and system aimed at enhancing timing closure in chip design. The patent, which is titled "Timing closure in chip design," discloses a method that involves identifying a critical timing path in a chip design pattern. The method focuses on determining variations in each segment of the critical timing path, which indicates the uncertainty of delay caused by various factors. By adjusting segments of the critical timing path based on these variations, the method effectively enlarges the timing window, thereby achieving timing closure in the design pattern. He has 1 patent to his name.

Career Highlights

Chen Du is associated with International Business Machines Corporation (IBM), where he applies his expertise in chip design. His work has been instrumental in advancing the efficiency and reliability of chip designs in various applications.

Collaborations

Throughout his career, Chen has collaborated with notable colleagues, including Hongwei (Nick) Dai and Xian He. These collaborations have further enriched his contributions to the field.

Conclusion

In summary, Chen Du is a key figure in the realm of chip design, with a focus on improving timing closure through innovative methods. His work continues to influence advancements in technology and chip design practices.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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