Perak, Malaysia

Chee Hoo Lee


Average Co-Inventor Count = 2.3

ph-index = 3

Forward Citations = 21(Granted Patents)


Location History:

  • Perak, MY (2006 - 2008)
  • Taiping, MY (2010)

Company Filing History:


Years Active: 2006-2010

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3 patents (USPTO):Explore Patents

Title: Chee Hoo Lee: Innovator in Integrated Circuit Packaging

Introduction

Chee Hoo Lee is a notable inventor based in Perak, Malaysia. He has made significant contributions to the field of integrated circuit packaging, holding a total of 3 patents. His work focuses on improving the efficiency and effectiveness of integrated circuit die configurations.

Latest Patents

One of Chee Hoo Lee's latest patents involves an innovative integrated circuit die configuration for packaging. This patent details terminal arrangements and configurations for mounting an integrated circuit die on a package substrate. The design aims to reduce package transmission paths. In one embodiment, terminals for signals sensitive to trace length outside a die are strategically arranged at the corners of the die. The die is mounted on a package substrate at an angle, directing the corners of the die towards the edges of the substrate. This approach minimizes trace length outside the die. Additionally, the center of the die may or may not align with the center of the substrate. Notably, this method does not significantly affect substrate warpage compared to a centered, non-rotated die mounting position.

Career Highlights

Chee Hoo Lee is currently employed at Intel Corporation, where he continues to innovate in the field of integrated circuits. His work has garnered attention for its practical applications in enhancing circuit performance.

Collaborations

Some of his notable coworkers include Chee Wai Wong and Jianggi He, who contribute to the collaborative environment at Intel Corporation.

Conclusion

Chee Hoo Lee's contributions to integrated circuit packaging demonstrate his commitment to innovation and excellence in technology. His patents reflect a deep understanding of the complexities involved in circuit design and packaging.

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