Toufen, Taiwan

Chao-Hsuan Hsu

This inventor holds 1 USPTO granted patent. Top assignee: Chang Gung University. Active years: 2009.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Chao-Hsuan Hsu. Retrieved from https://idiyas.com/inventor/chao-hsuan-hsu

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank

Average Co-Inventor Count = 4.0

ph-index = 1

Forward Citations = 3(Granted Patents)


Company Filing History:


Years Active: 2009

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1 patent (USPTO):Explore Patents

Title: Innovations of Chao-Hsuan Hsu in VLSI Circuit Design

Introduction

Chao-Hsuan Hsu is a notable inventor based in Toufen, Taiwan. He has made significant contributions to the field of Very Large Scale Integration (VLSI) circuit design. His innovative methods have the potential to enhance the accuracy and efficiency of circuit design processes.

Latest Patents

Chao-Hsuan Hsu holds a patent for a method of estimating the signal delay in a VLSI circuit. This method accurately estimates the delay and conversion time of a transmission signal within the circuit. It aims to prevent designers from making erroneous judgments regarding the logic implemented in the designed circuit. This patent showcases his expertise and commitment to advancing technology in the field.

Career Highlights

Chao-Hsuan Hsu is affiliated with Chang Gung University, where he contributes to research and development in VLSI technology. His work at the university allows him to collaborate with other experts in the field and further his research endeavors.

Collaborations

Chao-Hsuan Hsu has worked alongside notable colleagues, including Ming-Hong Lai and Chia-Chi Chu. Their collaborative efforts contribute to the advancement of knowledge and innovation in VLSI circuit design.

Conclusion

Chao-Hsuan Hsu's contributions to VLSI circuit design through his innovative patent demonstrate his dedication to improving technology in this field. His work continues to influence the way designers approach circuit logic and signal delay estimation.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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