Liaoning, China

Chao Gao

This inventor holds 1 USPTO granted patent and 1 published patent application. Top assignee: Intel Ndtm US LLC. Active years: 2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Chao Gao. Retrieved from https://idiyas.com/inventor/chao-gao-8cr35ns2

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 1 

% Patents Active = 100.0

Average Co-Inventor Count = 5.0

ph-index = 1


Company Filing History:


Years Active: 2026

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1 patent (USPTO):Explore Patents

Title: Chao Gao and a Patent for 3D NAND Wordline Contacts.

Introduction

Chao Gao is an inventor associated with Liaoning, China, and Intel NDTM US LLC. His patent work addresses a fabrication challenge in vertical 3D NAND memory: forming reliable electrical contacts to wordlines in staircase regions.

Latest Patents

The supplied information lists one patent for Chao Gao: “Selective Etch Stop for Wordline Contacts in Vertical 3D NAND Staircase Regions.” The disclosed structure includes vertical 3D NAND strings, a staircase region, a horizontal polysilicon wordline, and a vertical contact that connects to the wordline. An etch-stop material surrounds the contact and covers the wordline, extending to the step’s outside corner while remaining absent from the step sidewall and undercut at the corner. The patent describes embodiments of this arrangement and related implementations. Gao is credited with 1 patent in the information provided.

Career Highlights

Gao’s listed patent is focused on semiconductor memory manufacturing and the design of wordline contacts for 3D NAND devices. The supplied information associates him with Intel NDTM US LLC.

Collaborations

The supplied information names Hongpeng Yu and Yong Chen as Gao’s coworkers. It does not specify their roles in the patent or describe particular collaborative contributions.

Conclusion

Chao Gao’s listed invention concerns an etch-stop design intended to support wordline contact formation in vertical 3D NAND staircase regions, reflecting a focused contribution to semiconductor memory technology.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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