Tucson, AZ, United States of America

Chandrakant Patadia

This inventor holds 1 USPTO granted patent. Top assignee: Texas Instruments Corporation. Active years: 2003.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Chandrakant Patadia. Retrieved from https://idiyas.com/inventor/chandrakant-patadia

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank

% Patents Active = 100.0

Average Co-Inventor Count = 2.0

ph-index = 1

Forward Citations = 3(Granted Patents)


Company Filing History:


Years Active: 2003

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1 patent (USPTO):Explore Patents

Title: Chandrakant Patadia and Semiconductor Process Innovation.

Introduction

Chandrakant Patadia is an inventor associated with Tucson, Arizona, and Texas Instruments Corporation. His patent work addresses the processing of nichrome resistors in semiconductor manufacturing.

Latest Patents

The provided information lists one patent for Patadia: “Control of Nichrome Resistor Temperature Coefficient Using RF Plasma Sputter Etch.” The method describes processing a partially fabricated semiconductor wafer with patterned nichrome resistors. It includes wet pre-metallization cleaning, RF argon plasma sputter etching, and transferring the wafer between reactors without breaking vacuum before metal deposition. The process then patterns the metal interconnections, stabilizes the wafer through bake cycles, measures the resistor material’s temperature coefficient of resistance (TCR), and rejects the wafer if its measured TCR exceeds a predetermined value. Patadia is credited with 1 patent in the supplied data.

Career Highlights

Patadia’s listed invention focuses on controlling nichrome resistor TCR during semiconductor wafer processing. The described sequence combines surface preparation, plasma etching, metal deposition, stabilization, and measurement to support quality control.

Collaborations

The supplied information identifies Texas Instruments Corporation as Patadia’s company and Rajneesh Jaiswal as his coworker. No further details about their specific collaboration are provided.

Conclusion

Chandrakant Patadia’s listed patent presents a semiconductor fabrication method for managing nichrome resistor temperature characteristics and screening wafers against a specified TCR limit.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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