Karnataka, India

Chaitanya Ravindra Peddawad

This inventor holds 3 USPTO granted patents. Top assignee: International Business Machines Corporation. Active years: 2020-2021.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Chaitanya Ravindra Peddawad. Retrieved from https://idiyas.com/inventor/chaitanya-ravindra-peddawad

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank

Average Co-Inventor Count = 5.9

ph-index = 1

Forward Citations = 2(Granted Patents)


Location History:

  • Karnataka, IN (2020 - 2021)
  • Bengaluru, IN (2021)

Company Filing History:


Years Active: 2020-2021

Loading Chart...
3 patents (USPTO):Explore Patents

Title: **Chaitanya Ravindra Peddawad: Innovator in Integrated Circuit Design**

Introduction

Chaitanya Ravindra Peddawad hails from Karnataka, India, and has made significant contributions to the field of electronic design automation with his innovative inventions. With three patents to his name, he is recognized for his unique approach to optimizing digital integrated circuits.

Latest Patents

Chaitanya's latest patents include advancements that enhance the efficiency of electronic design automation. His first patent, titled "Efficient projection-based adjustment evaluation in static timing analysis of integrated circuits," introduces an electronic data structure in the form of a timing graph that characterizes an integrated circuit design. The process involves identifying key elements within the timing graph that require adjustments and calculating deterministic timing adjustments for various corner cases. This innovative approach significantly improves how timing adjustments are applied and managed in circuit design.

Another critical invention, "Feedback-aware slack stealing across transparent latches empowering performance optimization of digital integrated circuits," focuses on the efficiency of electronic logic circuit design. In this patent, at least one transparent latch is selected as a candidate for slack stealing, where the initial timing slack is assessed. If the initial timing slack is insufficient, a novel method determines whether it is on a feedback path, potentially replacing it with a next worse slack for enhanced performance.

Career Highlights

Chaitanya is currently employed at International Business Machines Corporation (IBM), where he continues to work on innovative solutions within the realm of electronic design. His role supports the development of cutting-edge technologies in integrated circuit performance, solidifying his reputation as a forward-thinking inventor.

Collaborations

Working alongside notable colleagues such as Kerim Kalafala and Jeffrey G Hemmett, Chaitanya has collaborated with some of the leading minds in his field. These partnerships have fostered an environment of creativity and innovation, enhancing the development of technologies that push the boundaries of electronic design.

Conclusion

Chaitanya Ravindra Peddawad stands out as an inventor making significant contributions in the domain of integrated circuits. Through his innovative patents and collaborative efforts at IBM, he continues to shape the future of electronic design automation, demonstrating the powerful impact of ingenuity and dedication in the field of technology.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
Loading…