Suwon-si, South Korea

Chae Ho Kim

This inventor holds 2 USPTO granted patents and 2 published patent applications. Top assignee: Samsung Electronics Co., Ltd.. Active years: 2017-2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Chae Ho Kim. Retrieved from https://idiyas.com/inventor/chae-ho-kim

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 2 

% Patents Active = 100.0

Average Co-Inventor Count = 4.8

ph-index = 1

Forward Citations = 2(Granted Patents)


Company Filing History:


Years Active: 2017-2026

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2 patents (USPTO):Explore Patents

Title: Chae Ho Kim and a Nonvolatile Memory Device with an MILC Channel.

Introduction

Chae Ho Kim is an inventor associated with Samsung Electronics Ltd. in Suwon-si, South Korea. The supplied information credits Kim with 1 patent concerning memory-device technology.

Latest Patents

Kim’s listed patent, “Nonvolatile Memory Device with MILC Channel,” describes a memory structure with alternating gate electrodes and insulating patterns. An information-storage film lines a trench that passes through these layers, and a semiconductor pattern is formed over the film. The semiconductor pattern consists of monocrystalline silicon regions, with metal silicide located at the grain boundary between them and absent from the interiors of those regions. The description also refers to volatile and nonvolatile memory devices.

Career Highlights

The available information identifies Kim’s work at Samsung Electronics Ltd. and highlights the patent’s focus on a metal-induced lateral crystallization (MILC) channel structure for memory devices.

Collaborations

The supplied data names Si Yeong Yang and Kwang Min Park as Kim’s coworkers. It does not specify their roles or describe particular joint patent work.

Conclusion

Chae Ho Kim’s listed patent reflects work on semiconductor structures for memory devices, including a channel design that places metal silicide at silicon grain boundaries.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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