El Dorado Hills, CA, United States of America

Buderya S Acharya


Average Co-Inventor Count = 5.8

ph-index = 2

Forward Citations = 17(Granted Patents)


Company Filing History:


Years Active: 2008-2011

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2 patents (USPTO):Explore Patents

Title: Innovations by Buderya S Acharya

Introduction

Buderya S Acharya is a notable inventor based in El Dorado Hills, California. He has made significant contributions to the field of technology, particularly in the area of chipsets and memory management. With a total of 2 patents, his work has had a considerable impact on the industry.

Latest Patents

Acharya's latest patents include "Multi-node chipset lock flow with peer-to-peer non-posted I/O requests" and "High performance chipset prefetcher for interleaved channels." The first patent focuses on systems and methods for managing transactions, specifically addressing the handling of non-posted transactions at I/O hubs. This innovation allows for halting inbound ordering queues and flushing transactions efficiently. The second patent presents an apparatus and method for prefetching data from memory devices with interleaved channels. It includes a stride detector, prefetch injector, and a scheduler that operates in a DRAM-state aware manner, enhancing the performance of memory access.

Career Highlights

Buderya S Acharya is currently employed at Intel Corporation, where he continues to develop cutting-edge technologies. His work at Intel has positioned him as a key player in advancing chipset technology and memory management solutions.

Collaborations

Throughout his career, Acharya has collaborated with esteemed colleagues, including Robert G Blankenship and Robert J Greiner. These partnerships have fostered innovation and contributed to the successful development of his patented technologies.

Conclusion

Buderya S Acharya's contributions to technology through his patents and work at Intel Corporation highlight his role as an influential inventor in the field. His innovations continue to shape the future of chipset and memory management technologies.

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