Intel Corporation

Buderya S Acharya

Robert G Blankenship

Robert J Greiner

Randy B Osborne

Zohar Bogin

Kenneth C Creta

Herbert H J Hum

Abhishek Singhal

Raul N Gutierrez

Hemant G Rotithor

Surya Kareenahalli

Systems and methods of managing transactions provide for receiving a first flush command at a first I/O hub, wherein the first flush command is dedicated to non-posted transactions. One embodiment further provides for halting an inbound ordering queue of the first I/O hub with regard to non-posted transactions in response to the first flush command and flushing a non-posted transaction from an outgoing buffer of the first I/O hub to a second I/O hub while the inbound ordering queue is halted with regard to non-posted transactions.

Multi-node chipset lock flow with peer-to-peer non-posted I/O requests

The invention comprises an apparatus and method of prefetching from a memory device having interleaved channels. The chipset prefetcher comprises a stride detector to detect a stride in a stream, a prefetch injector to insert prefetches onto the memory device, a channel mapper to map the prefetches to each channel of the memory device, a scheduler to schedule the prefetches onto the memory device in a DRAM-state aware manner, a throttling heuristic to scale the number of prefetches, and a prefetch data buffer to store prefetch data. The method of prefetching comprises tracking the state of streams, detecting a stride on one of the streams, selecting the stream with the stride for prefetch injection, enqueueing prefetches from the selected stream, mapping the prefetches to each of the interleaved channels, injecting the prefetches from the selected stream into each of the interleaved channels, and scheduling the prefetches onto the memory device in a DRAM-state aware manner.

High performance chipset prefetcher for interleaved channels

Growing community of inventors

El Dorado Hills, CA, United States of America

Buderya S Acharya