San Jose, CA, United States of America

Brian Swanson

This inventor holds 1 USPTO granted patent. Top assignee: Advanced Micro Devices Corporation. Active years: 2007.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Brian Swanson. Retrieved from https://idiyas.com/inventor/brian-swanson-0b8swon0

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank

% Patents Active = 100.0

Average Co-Inventor Count = 3.0

ph-index = 1

Forward Citations = 5(Granted Patents)


Company Filing History:


Years Active: 2007

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1 patent (USPTO):Explore Patents

Title: Brian Swanson: Semiconductor Process Innovation

Introduction

Brian Swanson is an inventor based in San Jose, California. His patent work addresses semiconductor fabrication, with a focus on forming halo implants while limiting their effect on junction capacitance.

Latest Patents

Swanson is associated with 1 patent: “Method and System for Providing Halo Implant to a Semiconductor Device with Minimal Impact to the Junction Capacitance.” The invention describes using a thin photoresist layer as a mask during halo implantation. By covering much of the active area, including the source and drain regions, the layer helps control which areas are exposed to the implant. The disclosed approach also accounts for height variations and implant angle, aiming to deliver the implant to targeted transistors while limiting the dose near trench edges.

Career Highlights

Swanson is associated with Advanced Micro Devices Corporation. His patent reflects work on semiconductor manufacturing techniques intended to manage implant placement and reduce unwanted effects on device characteristics.

Collaborations

The provided information identifies Zoran Krivokapic and Ahmad Ghaemmaghami as Swanson’s coworkers. Their specific roles in the patent or related work are not stated.

Conclusion

Brian Swanson’s patent documents an approach to halo implantation that uses a thin photoresist mask to control implant exposure and minimize impact on junction capacitance.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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