IDiyas

For the Inventor, By the Inventor

San Francisco, CA, United States of America

Brian P Lilly

USPTO Granted Patents = 40 

 

Average Co-Inventor Count = 4.0

ph-index = 6

Forward Citations = 174(Granted Patents)


Location History:

  • Urbana, IL (US) (2015 - 2016)
  • Los Gatos, CA (US) (2020)
  • San Francisco, CA (US) (2010 - 2024)

Company Filing History:

goldMedal37 out of 40,816 
 
Apple Inc.
 patents
silverMedal3 out of 832,680 
Other
 patents

Years Active: 2010-2025

where 'Filed Patents' based on already Granted Patents

40 patents (USPTO):
1. 12332792 - Scalable cache coherency protocol (2025-06-17),
2. 12216578 - Request ordering in a cache (2025-02-04),
3. 11947457 - Scalable cache coherency protocol (2024-04-02),
4. 11893241 - Variable hit latency cache (2024-02-06),
5. 11868258 - Scalable cache coherency protocol (2024-01-09),
6. 11768690 - Coprocessor context priority (2023-09-26),
7. 11741009 - Request ordering in a cache (2023-08-29),
8. 11544193 - Scalable cache coherency protocol (2023-01-03),
9. 11210104 - Coprocessor context priority (2021-12-28),
10. 11138111 - Parallel coherence and memory cache processing pipelines (2021-10-05),
11. 10795818 - Method and apparatus for ensuring real-time snoop latency (2020-10-06),
12. 9563575 - Least recently used mechanism for cache line eviction from a cache memory (2017-02-07),
13. 9563567 - Selective cache way-group power down (2017-02-07),
14. 9529730 - Methods for cache line eviction (2016-12-27),
15. 9513693 - L2 cache retention mode (2016-12-06),

Title: Brian P Lilly: Innovator in Cache and Memory Protocols

Introduction: Brian P Lilly, based in San Francisco, CA, is a prominent inventor with an impressive portfolio comprising 36 patents. His contributions primarily focus on advancements in cache management and memory protocols, which play a crucial role in enhancing computing efficiency.

Latest Patents: Some of Brian's latest inventions include groundbreaking patents such as "Request Ordering in a Cache" and "Scalable Cache Coherency Protocol." The "Request Ordering in a Cache" patent involves a sophisticated architecture for handling device requests through a multi-pipe caching system. The design addresses the challenges of maintaining request order efficiently and utilizes a two-level token store to track device requests. On the other hand, the "Scalable Cache Coherency Protocol" patent introduces a method for managing cache block coherence in systems with multiple agents and memory controllers, incorporating advanced directory management to avoid race conditions during memory access.

Career Highlights: Brian has made significant contributions while working at Apple Inc., where his innovative approaches to cache and memory protocols have elevated system performance. His extensive expertise in computer architecture and memory management has been instrumental in the development of more efficient computing solutions.

Collaborations: Throughout his career, Brian has collaborated with esteemed coworkers such as Hari Kannan and Ramesh B Gunna. These partnerships have enabled the exchange of ideas and fostered innovation, leading to the development of cutting-edge technologies.

Conclusion: Brian P Lilly's impressive array of patents underlines his role as an influential inventor in the field of computer science. His work continues to impact technology, promoting advancements in cache management and system efficiency at Apple Inc. As technology evolves, Brian's contributions remain significant, paving the way for future innovations in computing.

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