The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 05, 2021

Filed:

Sep. 12, 2018
Applicant:

Apple Inc., Cupertino, CA (US);

Inventors:

Muditha Kanchana, San Jose, CA (US);

Srinivasa Rangan Sridharan, San Jose, CA (US);

Harshavardhan Kaushikkar, San Jose, CA (US);

Sridhar Kotha, San Jose, CA (US);

Brian P. Lilly, San Francisco, CA (US);

Assignee:

Apple Inc., Cupertino, CA (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 12/0815 (2016.01); G06F 12/0884 (2016.01); G06F 12/0855 (2016.01);
U.S. Cl.
CPC ...
G06F 12/0815 (2013.01); G06F 12/0855 (2013.01); G06F 12/0884 (2013.01); G06F 2212/1032 (2013.01); G06F 2212/621 (2013.01);
Abstract

Systems, apparatuses, and methods for performing coherence processing and memory cache processing in parallel are disclosed. A system includes a communication fabric and a plurality of dual-processing pipelines. Each dual-processing pipeline includes a coherence processing pipeline and a memory cache processing pipeline. The communication fabric forwards a transaction to a given dual-processing pipeline, with the communication fabric selecting the given dual-processing pipeline, from the plurality of dual-processing pipelines, based on a hash of the address of the transaction. The given dual-processing pipeline performs a duplicate tag lookup in parallel with a memory cache tag lookup for the transaction. By performing the duplicate tag lookup and the memory cache tag lookup in a parallel fashion rather than in a serial fashion, latency and power consumption are reduced while performance is enhanced.


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