Taipei City, Taiwan

Bo-Yu Lai

This inventor holds 1 USPTO granted patent and 1 published patent application. Top assignee: Taiwan Semiconductor Manufacturing Co., Ltd.. Active years: 2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Bo-Yu Lai. Retrieved from https://idiyas.com/inventor/bo-yu-lai-1ymqgriv

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 1 

Average Co-Inventor Count = 1.0


Company Filing History:


Years Active: 2026

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1 patent (USPTO):Explore Patents

Title: Bo-Yu Lai and Semiconductor Process Innovation.

Introduction

Bo-Yu Lai is an inventor associated with Taipei City, Taiwan. His patent work concerns FinFET device design and methods for reducing parasitic capacitance in semiconductor structures.

Latest Patents

The supplied information lists one patent for Lai: “Low-K Gate Spacer and Methods for Forming the Same.” The disclosure describes FinFET gate spacers formed through two or more depositions, using different materials at different processing stages. This approach is intended to reduce parasitic capacitance between gate structures and contacts introduced after source/drain epitaxy growth. Lai’s listed portfolio includes 1 patent.

Career Highlights

Lai is associated with Taiwan Semiconductor Manufacturing Co., Ltd. His listed patent reflects work on semiconductor fabrication techniques, particularly gate-spacer structures designed to improve electrical performance in FinFET devices.

Collaborations

The supplied information identifies Li Chun Te as Lai’s coworker. Their association is noted alongside Lai’s work connected with Taiwan Semiconductor Manufacturing Co., Ltd.

Conclusion

Bo-Yu Lai’s listed invention addresses parasitic capacitance in FinFET devices through a multi-deposition gate-spacer approach, highlighting a focused contribution to semiconductor process innovation.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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